1. Technical Field
The present disclosure relates to a process for manufacturing a memory device including a vertical bipolar junction transistor and a MOS transistor with spacers. In particular, the disclosure refers to the manufacture of circuitry transistors and an array of selectors in a phase change memory (PCM) device, without being limited thereto.
2. Description of the Related Art
As is known, phase change memories are formed by memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element and a selection element. A memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum between completely amorphous and completely crystalline states.
Typical materials suitable for the phase change region of the memory elements include various chalcogenide elements. The state of the phase change materials is non-volatile, absent application of excess temperatures, such as those in excess of 150° C., for extended times. When the memory is set in either a crystalline, semicrystalline, amorphous, or semiamorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed.
Selection elements may be formed according to different technologies, for example they can be implemented by diodes, by MOS transistors or bipolar transistors.
U.S. Pat. No. 7,227,171 discloses a method for manufacturing memory devices including circuitry MOS transistors and array selection transistors. In detail, the circuitry MOS transistors are formed by growing an oxide layer onto the entire surface of the substrate; and deposing a polysilicon layer on the oxide layer. The polysilicon layer is then defined, to form gate regions of the periphery transistors; the polysilicon layer is completely removed from the array area. Then, LDD implants are carried out for the transistors; a salicide protection mask is formed to completely cover the array portion; a dielectric material (oxide) is deposed onto the whole wafer and etched, to form spacers on the sides of the gate regions of the circuitry MOS transistors; source and drain regions for the circuitry MOS transistors are implanted and salicide regions are grown over the gate regions and the source and drain regions in the circuitry area.
Then, after removing the salicide protection mask, collector regions and base regions of the selection bipolar transistors are implanted in the array area; the substrate is covered by a dielectric layer; the dielectric layer is etched to form contact; emitter and base contact regions are implanted in the substrate through the contact; conductive contact regions are formed in the contact; then phase change memory elements are formed above the selection bipolar transistors.
In order to simplify the etching of the contact and make such etching controllable to the same extent in all regions of the memory device, as well as to reduce the contact resistance of the junctions of the selection bipolar transistors, it has been already proposed to form salicided junctions also in the array area (see US Patent Application Publication No. 2007/0254446). To this end, after formation of the gate and the LDD regions of the circuitry MOS transistors a dielectric layer is deposited and etched to form spacers in the circuitry area and a silicide protection mask in the array area, covering selective portions of the array area. Then using suitable mask in addition to the silicide protection mask, emitters and base contacts of the selection bipolar transistors as well as source and drain regions of the MOS transistors are implanted.
However, the formation of the dielectric spacers in the circuitry area and of the silicide protection mask in the array area has proved troublesome. In fact, the lateral width of the dielectric spacers is strictly dependent on the thickness of the dielectric layer. As a consequence, the spacer width and the silicide protection mask thickness are dependent on one another; however, they are subjected to conflicting requirements. In fact, if the thickness of the dielectric layer is selected so as to obtain a desired length of the dielectric spacers, such a thickness is excessive for the silicide protection mask that cannot be defined without damaging the already defined structures in the circuitry area. On the other hand, if the thickness is selected according to the requirements of the silicide protection mask, the spacers would be too narrow, and such as not to ensure the correct geometrical characteristics needed for the circuitry MOS transistors. Therefore, a compromise solution has to be used, which however does not ensure optimal conditions in any of the circuitry or the array area.